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Descrição do livro
Verification is not a phase you bolt on after design — it's the thread that builds the system. And at SoC scale, it has to emerge.
Modern SoCs have outgrown the methodologies built for a simpler era. Drawing on twenty-five years and many chip tape-outs, Emergent Hardware Verification carries a single executable model from specification through formal proof, transaction-level modeling, and constrained-random stimulus all the way onto the FPGA emulator — one model across many substrates, with no rewrite at each boundary.
It takes an unsparing look at where UVM breaks down as designs scale, and builds an alternative on the actor model: verification components that are themselves synthesizable finite-state machines, wired by declarative typed topology, and rendered without change from SystemVerilog simulation to C++ to RTL gates.
Inside the book:
- Six worked RTL designs, each paired with its formal (SVA) contract
- From-scratch proof engines — CDCL, BMC, k-induction, IC3/PDR, interpolation, SMT — taught by building them
- A complete actor verification framework in SystemVerilog, C++, and SystemC
- Constrained-random stimulus synthesized onto hardware
- A chip-scale OpenTitan (Earl Grey) case study — behavioral model to real RTL, one actor graph
- FPGA emulation: turning the actor testbench itself into hardware
For design and verification engineers who have met the complexity wall firsthand and want a ground-up rethink — formal methods, TLM, UVM, and emulation reassembled around one idea: choose the right model of computation once, and let verification emerge with the system.
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